Method and apparatus for addressing a memory at selectively controlled rates

ABSTRACT

A memory contains digital data of related informational content in a plurality of discrete locations identified by respective addresses. The memory is addressed, or accessed, at a rate which depends upon the desired spacing between data from the various locations as it is sequentially read from the memory. In a specific embodiment, the data constitutes amplitude values of a complex waveform of the type produced by a musical instrument, at equally spaced points in time along an axis of the waveform. Apparatus for addressing the memory at any of a plurality of selectively controlled rates includes a calculator for continuously computing a set of numbers each defining a different spacing between the data during readout of the memory. When a desired rate of readout is selected, as by selecting a desired frequency of repetition of a complete cycle of the stored waveform, the number associated with that rate is sampled from the computed set and is periodically increased by its own value to identify appropriate data addresses in the memory, for accessing that data, at intervals of the periodic increase corresponding to the desired rate of readout.

Watson METHOD AND APPARATUS FOR ADDRESSING A MEMORY AT SELECTIVELYCONTROLLED RATES [75] Inventor: George A. Watson, Tustin, Calif. [73]Assignee: North American Rockwell Corporation, El Segundo, Calif. [22]Filed: Aug. 11, 1971 [21] Appl. No.: 170,992

Related US. Application Data [62] Division of Ser. No. 875,178, Nov. 10,1969, Pat. No.

[52] U.S. Cl. 84/1.0l, 84/103 [51] Int. Cl. GlOh /00 [58] Field ofSearch 84/1.0l, 1.03; 340/1725 [56] References Cited UNITED STATESPATENTS 3,163,850 12/1964 Austin et a1. 340/1725 3,267,433 8/1966Falkoff 340/1725 3,328,770 6/1967 Silver 340/1725 3,337,852 8/1967 Leeet a1 340/1725 3,417,378 12/1968 Simonsen et a1. 340/1725 3,696,201/1972 Arsem et al. 84/].01

3,697,661 10/1972 Deutsch 84/l.0l

3,700,781 10/1972 Obayashi 84/l.01

3,515,792 6/1970 Deutsch.... 84/103 3,610,799 10/1971 Watson 84/1.0l

[ l l l 3,743,755 July 3, 1973 [57] ABSTRACT A memory contains digitaldata of related informational content in a plurality of discretelocations identified by respective addresses. The memory is addressed,or accessed, at a rate which depends upon the desired spacing betweendata from the various locations as it is sequentially read from thememory. In a specific embodiment, the data constitutes amplitude valuesof a complex waveform of the type produced by a musical instrument, atequally spaced points in time along an axis of the waveform. Apparatusfor addressing the memory at any of a plurality of selectivelycontrolled rates includes a calculator for continuously computing a setof numbers each defining a different spacing between the data duringreadout of the memory. When a desired rate of readout is selected, as byselecting a desired frequency of repetition of a complete cycle of thestored waveform, the number associated with that rate is sampled fromthe computed set and is periodically increased by its own value toidentify appropriate data addresses in the memory, for accessing thatdata, at intervals of the periodic increase corresponding to the desiredrate of readout.

6 Claims, 12 Drawing Figures z'rno COUNT 0F j OCTAVE SECTION 3 "5mm"cou-T- iic /li 103 A READ-ONLY (185K MEMORY :01 CLOCK PULSES STORAGEREGISTER 106 we PHASE ANGLE PHASE ANGLE GATE L=: REGISTER NUMBER lL I09MULTlPLlER (by 2 SAMPLE POINT s ADDRESS I04 REGISTER ZERO cou-r 0FCOUNTER 3105a 110 OUTPUT TO D/A CONVER YER PATENIEBJHL 3 I973 SHEU 2 UF5 FROM 32 AND GATES 8 FROM I2 STAGES OF NOTE OF DECODER 7 SECTION 2(KEYBOARD COUNTER I) MULTIPLEXED SIGNAL 25 SWITCHING ARRAY N @L R 5 XAELK I EN C R) L m m m l s M Om U Mmv U M E 1. O 8 W H S 23 HP RRR RRcvSQu SS F. M II L R l n r: r! N w C II 2 FL {I L 0 Mll N I 1| M R l 8ER I: SA A U6 3 N m U W 6 UW Os PATENTEB JUL 3 I975 SHEET 3 (If 5 KEYCONTACT NOTES PLAYED) R4 TIME lREsEr COUNTER ZERO TONE GENERATORS (I-I2I GENERATOR ASSIGNMENT LOGIC MULTIPLEXED SIGNAL (SAMPLE POINTS)PAIENIEBJIIL aIsTs 3.743.755

CLAIM sELECT CLAIMEDI M SELECTZ I MASTER I I I I I I I I l I I I I l l lI I l l I l I I I I I MSELECTIZ MASTER CLoCK RESET MOD 384 ZERO COUNT i58 COUNTER COUNTER RESET KEY RELEASE 'NVERT SIGNAL To I\ ATTACI V 62DECAY LOGIC KEY DEPRESSED ET IBITI sET CLAIM IIIIIII TI II T MPERCUSSIVE SET CLAIMED I TO TONE CLAIM I CLAIM I GEN 28i CONTROL SELECT5 w 50 DECAY NOT CLAlMED 37 COMPLETE ZERO COUNT DETECTOR BACKGROUND OFTHE INVENTION The present invention is directed generally toward theaddressing of a memory containing digital data of related informationalcontent in successive or sequential data locations, or addresses,therein. The data may, for example, consist of digital samples of theamplitude of a waveform at successive selected points, or may consist ofa list of symbols identifying in a particular order the members of aclass of prescribed characteristics, or may consist of a mathematicalprogression of numbers, or may consist of other information.

It is sometimes necessary or desirable to read data from a memory unitin which it is stored at a controllably variable rate. For example, inthe case of stored amplitude samples of a waveform, the rate at whichthe samples are read from the memory can be used to determlne thefrequency of the output waveform, or the phase angle of the waveformrelative to a fixed reference. Alternatively, if the rate at whichsamples are read from the memory is held constant, the frequency of theoutput waveform may be varied by changing the rate at which the addresschanges. In the latter case, the same data may be read from the memoryseveral times in succession where the address is unchanged throughseveral access commands, so that the same memory location is addressedeach time. For certain types of stored data, no difficulty may beencountered with such a process. If the data in a specified memorylocation cannot be read out repetitively, without destroying thesignificance of the data, then special means must be devised to preventsupplying that data on a repeated basis to its ultimate processingcircuitry to ensure that the same data is supplied only once, during aspecific sequence, to subsequent processing circuitry.

SUMMARY OF THE INVENTION Broadly, the invention includes means forperforming a calculation to derive a number that determines the rate atwhich the memory shall be accessed, regardless of the consistency of theclock rate at which the overall system is operated. The calculatingmeans continuously calculates a'set of distinct and different numbers,and means are provided to select a desired number that will produce apredetermined rate ofaccessing of the memory based on the occurrence ofa related oneof a set of selected events. Thus, if an event occurs, thenumber with which that event is associated is selected and determinesthe rate at which the memory is accessed. Evey number is periodicallycalculated in cyclic sequence to ensure its availability when the eventwith which it is associated occurs. I

In a specific embodiment demonstrating an exemplary application of theinvention, a memory unit in a digital electronic musical instrument isaddressed at a rate which is selectively controllable according to thefrequency (or phase angle relative to a reference phase) of the note tobe produced by the instrument. The memory unit contains digital datarepresenting samples of the amplitude of a complex waveform at aplurality of uniformly spaced points in time (i.e., along the abscissa,or time axis, of the waveform). The complex waveform is identical foreach note, but its rate of cyclic repetition is to be varied accordingto the frequency of the note to be played. The individual amplitudesamples are stored in separate locations, preferably at sequentialaddresses although this is not absolutely necessary, of a read-onlymemory (ROM), and the memory is thereafter addressed, i.e., the storeddata is accessed or read out, at a rate which depends upon the frequencyof the note to be generated by the instrument.

In a digital electronic organ of the type specifically disclosed in thecopending application of George A. Watson entitled Multiplexing Systemfor Selection of Notes and Voices in an Electronic Musical Instrument,filed Oct. 30, 1969 and issued Oct. 5, 1971 as U. S. Pat. No. 3,610,799the instrument has a plurality of keyboards, including at least onemanual and at least one pedal division. Each keyboard may cover severaloctaves. When a key is depressed on any keyboard of the digitalelectronic organ, a sound waveform is to be generated with a periodicitycorresponding to the desired note frequency. The waveform is computed indigital format consisting of a series of digital words which representthe magnitude of the waveform at a series, or sequence, of uniformlyspaced sample points. The digital sample point values thus generated aresubsequently converted to analog form.

The sample points are preferably uniformly spaced because such a formatpermits the most direct analysis, and therefore the most directsynthesis, of the desired waveform. If desired, the uniform spacing ofsample points may be such that there is provided an integral number ofsamples per cycle for each note frequency to be generated. Such atechnique requires a sampling rate that varies directly with thefrequency. Alternatively, the samples may be spaced uniformly in time,in which case the number of sample points differs according tofrequency, and the phase angle between sample points varies with thefrequency of the note to be generated. Although the synthesis of amultiplicity of note frequencies can be implemented for eithertechnique, using a single clock frequency, the preferred frequencysynthesis technique is that in which the phase angle between the samplepoints varies with frequency, i.e., in which the sampling rate is fixedfor all note frequencies to be generated, and the various generated notefrequencies are produced as a result of the different phase angles.

According to a specific application of the memory addressing techniqueof the present invention, then, there is provided a means forcontinuously calculating phase angles, to make available to a selectionmeans any desired phase angle corresponding or related to a specificfrequency, the selection means being governed by frequency criteriadependent on the note associated with the depressed key. The selectionof a particular phase angle is translated into a sample point address inthe memory unit within which the digital values representing amplitudesamples of the waveform are stored.

As the phase angle changes, the rate at which the memory unit isaddressed changes. This is accomplished by providing an address registerto which the phase angle number is supplied, and which is incrementedaccording to the value of the phase angle number. That is to say, onceeach clock time, the phase angle number is added to the sample pointaddress register. Only a relatively small number of bits of rather lowsignificance in the latter register are used to designate the samplepoint addresses, and these bits are arranged to be incremented at a ratewhich depends upon the phase angle number, so that a new address may ormay not be specified for several periodic increases in theaddress-identifying word. In the limit, an actual sample point addressin the memory is identified and the memory is thereupon appropriatelyaccessed for retrieval of the data contained at those addresses, foreach increment dictated by the phase angle number. This limit is theuppermost note frequency that can be generated by the organ. For lowerfrequencies, the incrementing of the sample point address register issuch that new addresses are identified only after a corresponding numberof repetitions of the phase angle number, at the fixed clock frequency.

Accordingly, it is the principal object of this invention to provide amethod and apparatus for addressing a memory at any one of severalselectively controllable rates.

It is another object of this invention to provide methods and apparatusconsistent with the object set forth immediately above, in which thememory unit contains digital data of related information content, soarranged or so located that sequential addresses of the memory are to beread out in sequence.

Still another object of this invention is to provide a method andapparatus as set forth above, specifically for use in the tonegenerating system of a digital electronic musical instrument.

BRIEF DESCRIPTION OF THE DRAWINGS In describing the present invention,reference will be made to the accompanying figures of drawing, in which:

FIG. I is a simplified block diagram of a portion of a digitalelectronic organ system whose overall structure and functiondemonstrates a specific application of the controllable readout of amemory in accordance with the invention, in which portion a timedivision multiplexed signal is produced containing a recycling sequenceof time slots each associated with a particular key of the organ, thecontents of each time slot indicating whether the associated key hasbeen actuated;

FIG. 2 is a circuit diagram of an exemplary decoder for use in thesystem of FIG. I;

FIG. 3 is a more detailed circuit diagram of the switching array andencoder used in the system of FIG.

FIG. 3A is a circuit diagram of an alternative encoder to that shown inFIG. 3, for use in the system of FIG,

FIG. 4 is a circuit diagram of the input-output bus connecting means ateach intersection in the switching array of FIG. 3;

FIG. 5 is illustrative of a multiplexed waveform developed by the systemof FIG. 1 and responsive to actuation of selected keys;

FIG. 6 is a simplified block diagram of a generator assignment and tonegenerating apparatus for processing the multiplexed signal produced bythe system of FIG. I to develop the desired tones as an audible outputof the organ;

FIG. 7A and 7B together constitute a circuit diagram of one embodimentof the tone generator assignment logic for the system of FIG. 6;

FIG. 8A is a block diagram of a tone generator employing the principlesof the present invention with regard to selective rate of addressing amemory, for use with assignment logic of FIGS. 7A and 7B in the systemof FIG. 6;

FIG. 8B is a block diagram of an alternate embodiment of a portion ofthe tone generator of FIG. 8A; and

FIG. 9 is illustrative of a complex waveshape of the type produced by apipe organ, and of the sample points at which amplitude values are takenfor simulation at selected note frequencies.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, thekeyboard multiplexing system or note selection system includes akeyboard counter l which is implemented to provide a specified count foreach key of each keyboard (including manuals and pedal divisions) of theorgan. If, for example, the electronic organ in which the multiplexingsystem is used has four keyboards, such as three manuals and a pedalboard, each encompassing up to eight octaves, then keyboard counter 1should have the capability of generating 4 X 8 X 12 384 separate counts(digital words). It is essential that the counter be capable ofdeveloping a count representative of every key on every keyboard of theorgan; however, it may be desirable to provide a counter that canproduce a count greater than the number of available keys in order tohave available certain redundant counts not associated with any keys.Such redundancy is readily provided by simply utilizing a counter ofgreater capacity than the minimum required count.

Keyboard counter 1 is divided into three separate sections (or separatecounters) designated 2, 3 and 4. the first section (designated 2) isconstructed to count modulo 12 so as to designate each of the twelvekeys associated with the 12 notes in any octave. The second section(designated 3) is adapted to count modulo 8, to specify each of theeight octaves encompassed by any of the four keyboards. The last section(designated 4) is designed to count modulo 4 to specify each keyboard ofthe organ. Therefore, the overall keyboard counter is arranged to countmodulo 384, in that at the conclusion of every 384 counts, the entireset of keyboards have been covered (scanned) and the count repeatsitself. To that end, each counter section may be composed of a separateconventional ring counter, the three counters being connected in thetypical cascaded configuration such that when section 2 reaches itsmaximum count it advances the court of counter section 3 by one, andwill automatically initiate a repetition of its own count. Similarly,attainment of its maximum count by counter section 3 is accompanied byadvancement of the count of section 4 by one.

Advancement of the count of counter 2 is accomplished by application ofclock pulses thereto from a master clock source 5 which delivers clockpulses at a sufficiently rapid repetition rate (frequency) to ensureresolution of depression (actuation) and release (deactuation) of anykey on any keyboard, i.e., to supply a pulse at the instant of either ofthese events. Scanning of all keyboards of the organ at a rate of 200 ormore times a second is deemed quite adequate to obtain this desirableresolution. For the exemplary keyboard counter set forth above, this isequivalent to a minimum of 200 X 384 76,800 counts per second, so that amaster clock delivering clock pulses at a rate of 100 KC/s is quitesuitable.

A total of four lines emanate from counter 4, one line connected to eachring counter stage, to permit sensing of the specific keyboard which ispresently being scanned. Similarly, eight lines are connected to theeight ring counter stages, respectively, of octave counter 3 to detectthe octave presently being scanned.

Thus, a total of 12 lines extend from counters 3 and 4, and these twelvelines can carry signals indicative of 32 (8 X 4) possible states of thekeyboard counter. The specific one of the 32 states, representative of aparticular octave on a particular keyboard, which is presently beingscanned is determined by use of a decoder circuit 7 composed of 32 ANDgates designated 8-1, 8 2, 8-3, 8-32 (FIG. 2), each with two inputterminals and an output terminal. The gates are arranged in four groupsof eight each, with every gate of a particular group having one of itstwo input terminals (ports) connected to one of the four lines ofcounter 4. Distinct and different ones of the eight lines from counter 3are connected to the other input terminal of respective ones of theeight AND gates of that group. A corresponding situation exists for eachgroup of AND gates, with the only difference being that each group isassociated with a different output line of counter section 4. Using thisarrangement, the decoder logic designates every octave of keys in theorgan by a respective driver pulse when a count corresponding to thatoctave is presently contained in the counter.

The output pulses derived from the AND gates (or drivers) of decodercircuit 7 are supplied on respective ones of 32 bus bars (or simply,buses), generally designated by reference numeral 10, to a keyboardswitching array ll. From the preceding descripton, then, it will beclear that array 11 has one input bus 10 for every octave of keys in theorgan (including every octave on every keyboard), and that a drive pulsewill appear on each input bus approximately 200 times per second, theexemplary rate of scan of the keyboard, as noted above, for obtainingadequate resolution of operation of the keys. Switching array 11 alsohas twelve output buses, generally designated by reference number 12,each to be associated with a respective one of the twelve notes (andhence, the twelve keys) in any given octave.

Array llli is basically a diode switching matrix, in which spaced inputbuses It) and spaced output buses 12 are orthogonally arranged so thatan intersection or crossing occurs between each input bus and eachoutput bus (see FIG. 3), for a total of 384 intersections, one for eachcount of the keyboard counter 1. As is typical in this type of matrix,the crossed lines or buses are not directly interconnected. Instead, ajump diode, such as that designated by reference number 113 in FIG. 4,is connected between the input bus 10 and the output bus 12 at eachintersection, the diode poled for forward conduction (anode-to-cathode)in the direction from an input bus 10 to an output bus 12. Wired inseries circuit or series connection with each diode 13 is a respectiveswitch 14 which is normally open circuited and is associated with adistinct respective one of the keys of the organ, such that depressionof the associated key produces closure (close circuiting) of the switch14 whereas release of the associated key results in return of the switchto its open state. Alternatively,

each of switches 14 may itself constitute a respective key of thevarious keyboards of the organ.

While switch 14 is shown schematically as being of mechanical singlepole, single throw (SPST) structure, it will be understood that any formof switch, electronic, electromechanical, electromagnetic, and so forth,may be utilized, the exact nature of the switch depending primarily uponthe nature of the energization produced upon operation of the associatedkey. Switch 14, then, is adapted to respond to the particular form ofenerization or actuation produced upon operation of a key on anykeyboard (or, as observed above, may itself constitute the key), tocomplete the circuit connecting associated diode 13 between a respectiveinput bus 10 and a respective output bus 12 at the intersection of thosebuses, when the key is depressed, and to open the circuit connecting thediode between respective input and output buses at that intersectionwhen the key is released. Positive pulses occurring at the rate ofapproximately 200 per second, for example, according to the timingestablished by master clock 5, are transferred from input bus 10 tooutput bus 12 via the respective diode l3 and closed switch 14 when theassociated key is depressed. While a switch alone (i.e., without theseries connected diode) would serve the basic purpose of transferring asignal between the input and output lines of array 11, the diodeprovides a greater degree of isolation from sources of possibleinterference (noise) and acts to prevent feedback from output to inputlines.

In FIG. 3, the output buses 12 from switching array 11 are connected toan encoder circuit 15 to which are also connected the twelve outputlines, generally designated by reference number 16, from keyboardcounter section 2. To produce an orderly arrangement in which each keyof the organ is assigned a distinct and different time slot in atime-division multiplex waveform, the switches 14 associated with therespective keys are conveniently arranged in a specific sequence in theswitching array 11. Assume, for example, that a specific output bus 17of the switching array is to be associated with note A of any octave, asecond output bus 18 is to be associated with note B of any octave, andso forth. Then switches 14 in the row corresponding to output bus 17 inarray or matrix 11 are associated with the keys corresponding to thenote A in each octave of keys in the organ. The column position of eachswitch 14 in matrix I 1 corresponds to a specific octave of keys in theorgan, and hence, to a specific octave encompassed by a specifickeyboard of the organ.

Each of the output buses 12, including l7, l8, and so forth, isconnected to one of the two input ports or terminals of a respective ANDgate of the twelve AND gates 20-1, 20-2, 20-3, 20-12, of encoder circuit15. An output lead 16 of counter section 2 associated with the ringcounter stage designating the count for a particular note (key) in agiven octave is connected to the remaining port of an encoder circuitAND gate having as its other input a pulse on the output bus 12associated with that same note. A similar arrangement is provided foreach of the remaining eleven output lines 16 of counter section 2 withrespect to the AND gates 20 and the output buses 12. Thus, for example,if output bus 17 (associated with the row of switches 14 in matrix 1 lfor note A) is conected to one input terminal of AND gate 20-1, thenoutput line 22 from the stage of counter 2 designating the countassociated with note A is connected to the remaining input terminal ofgate 20-1. The output terminal of each of AND gates 20 is connected to arespective input terminal of OR gate 23, the output of the OR gateconstituting the output signal of the encoder circuit. By virtue of itsstructure, encoder circuit is effective to convert the parallel outputof array 11 to a serial output signal in accordance with the scanning ofoutput buses 12 as provided by the advancing and repeating count sensedin the form of pulses (at a-rate of about 200 per second) appearing onoutput lines 16. The end result of this circuitry is the production of atime-division multiplex (TDM) signal on a single conductor 25 emanatingfrom encoder 15.

As an alternative to the specific logic construction shown for encoder15 in FIG. 3, the encoder may have the circuit configuration exemplifiedby FIG. 3A. Referring to the latter Figure, the encoder includes a shiftregister 80 having twelve cascaded stages designated SR1, SR2, SR3,SR12, each connected to a respective output bus 12 of switching matrix11 to receive a respective output pulse appearing thereon. The shiftregister stages are loaded in parallel with the data read from switchingarray 11 on output buses 12, in response to each of the pulses appearing(i.e., each time a pulse appears) on one of the 12 output leads 16 ofnote counter 2. That one output of the note counter which is to supplythe load command for all twelve stages of shift register 80 is selectedto permit the maximum amount of settling time to elapse between eachadvance of octave counter 3 and keyboard counter 4 and the loading ofthe shift register. In other words, it is extremely desirable that thedata to be entered into the shift register from the switching array bestabilized to the greatest possible extent, and this is achieved byallowing the counters whose scanning develops this data, to settle atleast immediately prior to loading. Thus, the first note counter stage,or one of the early stages, is selected to provide load pulses to shiftregister 80.

Shift pulses are supplied to the shift register by master clock 5, whichalso supplies note counter 2, to shift the contents of each shiftregister stage to the next succeeding stage except during those bittimes when the shift pulse is pre-empted by a load pulse from the notecounter. Accordingly, shift register 80 is parallel loaded, and the datacontents of the register are then shifted out of the register in serialformat on encoder output line 25 until a one-bit pause occurs whenanother set of data is parallel loaded into the shift register, followedagain by serial readout on line 25. This serial pulse train constitutesthe time division multiplexed output signal of encoder 15 just as in theembodiment of FIG. 3, except that with the FIG. 3A configuration,decoder 7 (and the counters 3 and 4 supplying pulses thereto) undergo agreater amount of settling time.

It will be observed that this operation consitutes a parallel-to-serialconversion of the information on output buses 12 to a time-divisionmultiplexed waveform on the output line 25 of encoder 15.

In the TDM signal, each key has a designated time slot in the 384 timeslots constituting one complete scan of every keyboard of the organ. Inthe specific example of the time base provided by master clock 5, theTDM waveform (shown by way of example in FIG. 5) is initiated about 200times per second. This waveform contains all of the note selectioninformation, in serial digital form on a single output line, that hadheretofore required complex wiring arrangements. This waveformdevelopment will be more clearly understood from an example of theoperation of the circuitry thus far discussed. It should be observedfirst, however, that all of the counter and logic circuitry described upto this point can be accommodated within a very small volume of space byfabrication in integrated circuit form using conventionalmicroelectronic manufacturing techniques.

When the main power switch for the electronic organ is turned on, allcomponents are energized to an operational state, the master clockdelivering pulses to keyboard counter l at the aforementioned rate. Upondepression of a key on any keyboard of the organ, including the manualsand pedal divisions, a respective switch 14 associated in seriesconnection with a diode 13 at the intersection between the appropriateinput bus 10 and output bus 12 of the switching array 11 is closed,thereby connecting the two buses to supply pulses appearing on a givenbus 10 from decoder 7, to the appropriately connected output bus 12 forapplication to encoder 15. If, for example, the key that was depressedis associated with note C in the second octave, C appears in theappropriate time slot of the multiplexed signal emanating from encoderand will repetitively appear in that time slot in each scan of thekeyboards of the organ as long as that key is depressed. That is to say,a pulse appears on output line 10 of decoder 7 associated with thesecond octave in the manual being played, in accordance with the scanprovided by master clock 5, as the counter stage associated with thatoctave is energized in keyboard counter octave section 3 and the counterstage associated with that manual is energized in section 4 of thekeyboard counter. The connection between the appropriate input bus 10and output bus 12 of switching array 11 for the particular octave andkeyboard under consideration is effected by the depression and continuedoperation of the key associated with the switch 14 for that intersectionin the array. Since, as previously stated, each switch is associatedwith a particular note (key) and is positioned in a specific row of theswitching array, a signal level is thereby supplied to the appropriateoutput bus 12 of the switching array arranged to be associated with thatnote. Each time the specified note, here the note C, is scanned in thesequence of count in the note section 2 of the keyboard counter, asecond input is provided to the AND gate 20 receiving the signal levelon output bus 12, and a pulse is delivered to OR gate 23. By virtue ofthis operation, the pulse which appears at the output of OR gate 23always appears in the identical specified time slot in the multiplexedsignal for a specific note associated with a particular key on aparticular keyboard of the organ.

If more than one key is depressed, regardless of whether one or morekeyboards is involved, operation corresponding to that described abovefor a single depressed key is effected for every operated key. Thus, forexample, assume that the key associated with note C is played on onemanual, the note B is played on a second manual, and the notes D,,, Eand G are played on a third manual, the associated keys being depressedsubstantially simultaneously to produce desired simultaneousreproduction of all notes as the audio output of the organ. Under theseconditions, the associated switches 14 in the switching array 11 areclosed to provide through connections between the respective input buses10 and output buses 12 for the specific octaves and manuals involved. Asthe appropriate AND gates in encoder 15 are supplied with gating signalsfrom the sequentially energized counter stages of note section 2, duringthe scanning operation provided by that keyboard counter section, pulselevels appearing on output buses 12 for which switches 14 have beenclosed are gated in the appropriate time slots of the multiplex signalon the output lead from OR gate 23 of encoder 15, for the specific notesinvolved.

An example of the multiplex signal waveform thus generated is shown inFIG. 5. While the pulses appearing in the time slots associated with thespecific notes mentioned above are in a serial format or sequentialorder, their appearance is repetitive during the interval in which therespective keys are actuated. Hence, the effect is to produce asimultaneous reproduction of the notes as an audio output of the organ,as will be explained in more detail in connection with the descriptionof operation of the tone generation section.

Referring now to FIG. 6, the multiplexed signal arriving from encoder 15is supplied to generator assignment logic network 26 which functions toassign a tone generator 28 to a depressed key (and hence, to generate aparticular note) when the associated pulse first appears in itsrespective time slot in the multiplexed signal supplied to theassignment logic. If only 12 tone generators 28 are available in theparticular organ under consideration, for example, the assignments areto be effected in sequence (order of availability), and once particularpulses have been directed to all of the available generators (i.e., allavailable tone generators have been captured by respective noteassignments), the organ is in a state of saturation. Therafter, nofurther assignments can be made until one or more of the tone generatorsls released. The availability of 12 (or more) tone generators, however,renders it extremely unlikely that the organ would ever reach a state ofsaturation since it is quite improbable that more than twelve keys wouldbe depressed in any given instant of time during performance of amusical selection. The output waveforms from the captured tonegenerators at the proper frequencies for the notes being played, aresupplied as outputs to appropriate waveshaping and amplificationnetworks and thence to the acoustical output speakers of the organ. Ifthe tone generators 28 supply a digital representation of the desiredwaveform, as is the case in one embodiment to be described, then thedigital format is supplied to an appropriate digitalto-analog converter,which in turn supplies an output to the waveshaping network.

At any given instant of time, each tone generator 28 may be in only oneof three possible states, although the concurrent states of the tonegenerators may differ from one tone generator to the next. These threestates are as follows:

1. a particular note represented by a specific pulse in the multiplexedsignal has captured (i.e., claimed) the tone generator;

2. the tone generator is presently uncaptured (i.e., unclaimed oravailable), but wlll be captured by the next incoming pulse in themultiplexed signal associated with a note which is not presently a tonegenerator captor; and

3. the tone generator is presently available, and will not be capturedby the next incoming pulse.

It should be apparent from this delineation of possible states that anynumber of the tone generators provided (12, in this particular example)may be in one or the other of the states designated (1) and (3), above,but that only one of the tone generators can be in state (2) during agiven instant of time. That is, one and only one generator is the nextgenerator to be claimed. When the specific tone generator in state (2)is claimed by an incoming pulse, the next incoming pulse which is notpresently claiming a tone generator is to be assigned to the generatorthat has now assumed state (2). For example, if the third tone generator(No. 3) of the 12 generators is captured by an incoming pulse (noterepresentation) and the fourth generator (No. 4) was and still iscaptured by a previous note selection, then tone generator No. 4 isunavailable to the next incoming pulse, and the privilege of capturemust pass to the next tone generator which is not presently in a stateof capture. If all of the tone generators are captured, that is, all arein state (las described above, then the organ is saturated and nofurther notes can be played until at least one of the tone generators isreleased. As previously observed, however, the saturation of an organhaving 12 (or more) tone generators is highly unlikely. Generatorassignment system 26 is utilized to implement the logic leading to thedesired assignment of the tone generators 28, and thus to the threestates of operation described above. An exemplary embodiment of thegenerator assignment logic is shown in FIGS. 7A and 78. Referring toFIG. 7A, a ring counter 30, or a 12-bit recirculating shift register inwhich one and only one bit position is a logical l at any one time, isused to introduce a claim selection, i.e., to initiate the capture, ofthe next available tone generator in the set of tone generators 28provided in the organ. A shift signal appearing on line 32 advances the1 bit from one register or counter stage to the next, i.e., shifts the lto the next bit position. Each bit position is associated with andcorresponds to a particular tone generator, so that the presence of thelogical l in a particular bit position indicates selection of the tonegenerator to be claimed next, provided that it is not already claimed.

Each time the logical 1" appears in a stage of shift register 30, aclaim select signal appears on the respective output line 34 associatedwith the stage. This claim select signal is supplied in parallel to oneinput of a respective one of AND gates 35, on line 36, and to furtherlogic circuitry (to be described presently with reference to FIG. 78),on line 37. The output line of each of AND gates 35 is connected to aseparate and distinct input line of an OR gate 40 which, in turn,supplies an input to an AND gate 42 whose other input constitutes pulsesfrom the master clock 5.

In operation of the portion of the generator assignment logic shown inFIG. 7A, assume that shift register stage No. 2 contains the logical 1".That stage therefore supplies claim select 2" signal to the respectivelyassociated AND gate 35 and, as well, to further logic circuitry on line37. If this further logic circuitry determines that the associated notegenerator may be claimed, a claimed" signal is applied as the secondinput to the respectively associated AND gate 35. Since both inputs ofthat AND gate are now true" an output pulse is furnished via OR gate 40to the synchronization gate 42. The latter gate produces a shift pulseon line 32 upon simultaneous occurrence of the output pulse from OR gate40 and a clock pulse from master clock 5. Accordingly, the logical isadvanced one bit position, from stage No. 2 to stage No. 3 of shiftregister 30, in preparation for the claiming of the next tone generator.

Suppose, however, that the tone generator 28 corresponding to stage No.3 is already claimed by a previous note pulse in the multiplexed signal.In that event a claimed signal appears as one input to the associatedAND gate 35, and with the claim select signal appearing as the otherinput to that gate by virtue of stage No. 3 containing the singlelogical 1, another shift pulse is immediately generated on line 32 toadvance the logical 1 to stage No. 4 of the shift register. Similaradvancement of bit position of the 1" continues until an unclaimed tonegenerator is selected. If it should happen that no note is presentlybeing selected on a keyboard of the organ at the time when an unclaimedtone generator is selected, the l bit remains in the shift registerstage associated with the selected tone generator until such time as aclaimed signal is concurrently applied to the respective AND gate 35,Le, until the selected tone generator is claimed, because until thattime no further shift signals can occur.

Referring now to FIG. 73, each tone generator also has associatedtherewith a respective portion of the generator assignment logic asshown in that Figure. In other words, the circuitry of FIG. 78, withminor exceptions to be noted in the ensuing description, is associatedwith the ith tone generator (where i 1, 2, 3, l2), and since each ofthese portions of the assignment logic is identical, a single showingand description will suffice for all. An AND gate 50 has three inputs,one of which is the multiplexed signal deriving from encoder (this beingsupplied in parallel to the AND gates 50 of the remaining identicalportions of the assignment logic for the other tone generators, aswell), a second of which is the claim select signal appearing on line 37associated with the 11th stage of shift register 30 (FIG. 7A), and thethird of which is a signal, on line 52, indicating that the pulse in themultiplexed signal has not captured any tone generator as yet. Ofcourse, these signals are not present unless the respective events whichproduce them are actually occurring, but if all three signals aresimultaneously presented as inputs to AND gate 50, a set" signal isapplied to a claim flip-flop 53 to switch that flip-flop to the claimedstate and simultaneously therewith to supply a claimed signal to the ANDgate 35 associated with the 11th stage of shift register 30 and to therespectively associated tone generator 28.

A modulo 384 counter 55 is employed to permit recognition by therespective portion of the generator assignment logic of the continuedexistence in the multiplexed signal of the pulse (time slot) whichresulted in the capture of the associated tone generator. To that end,counter 55 is synchronized with keyboard counter I (also a modulo 384counter) by simultaneous application thereto of clock pulses from masterclock 5. The count of each counter 55 associated with an uncaptured tonegenerator is maintained in synchronism with the count of keyboardcounter l by application of a reset signal to an AND gate 58 each timethe keyboard counter assumes a zero count; i.e., each time the count ofthe keyboard counter repeats. However, that reset signal is effective toreset counter 55 only if the associated tone generator is uncaptured.The latter information is provided by the state of flip-flop 53, i.e., anot claimed signal is supplied as a second input to AND gate 58 wheneverflip-flop 53 is in the unclaimed state.

When the flip-flop and hence, the associated tone generator) is claimed,however, it is desirable to indicate the time slot occupied by the pulsewhich effected the capture, and for that reason a reset signal isapplied to counter 55 at any time that an output signal is derived fromAND gate 50. Thus, in the captured state, the zero count of counter 55occurs with each repetition of the capturing pulse in the TDM waveform.Such information is valuable for a variety of reasons; for example, toprevent capture of an already captured tone generator when the zerocount continues to appear simultaneously with a pulse in the TDMwaveform, and to provide a key released indication when the zero countis no longer accompanied by a pulse in the TDM waveform. Captureprevention is effected by feeding a signal representative of zero countfrom counter 55 to the appropriate input terminal of an OR gate 60associated with all of the tone generators and their respectivegenerator assignment logic. The logical l supplied to OR gate 60 isinverted so that simultaneous identical logical inputs cannot bepresented to AND gate 50. On the other hand, when the zero count ismerely snychronized with the zero count of the keyboard counter and isnot the result of capture of the associated tone generator it does notinterfere with subsequent capture of that tone generator since it doesnot occur simultaneously with a pulse in the TDM signal. A key releaseindication is obtained by supplying the zero count signal to an AND gate62 to which is also supplied any signal deriving from an inverter 63connected to receive inputs from the TDM signal. If the zero countcoincides with a pulse in the multiplexed signal, the inversion of thelatter pulse prevents an output from AND gate 62, and this is properbecause the coincidence of the zero count and the TDM pulse isindicative of continuing depression of the key which has captured thetone generator. Lack of coincidence is indicative that the key has beenreleased, and results in the key release signal. Scanning of thekeyboards is sufficiently rapid that any delay which might exist betweenactual key release and initiation of the key release signal isnegligible, and in any event is undetectable by the human senses.Furthermore, the generation of a false key release signal when the tonegenerator is presently unclaimed, as a result of the occurrence of azero count from counter 55 synchronized with the zero count of thekeyboard counter and the simultaneous absence of a pulse in the TDMsignal, can have no effect on the audio output of the organ since theassociated tone generator is not captured and is therefore notgenerating any tone. In any case, the key release signal deriving fromAND gate 62 is supplied to attackldelay logic of the tone generator toinitiate the decay of the generated tone.

The set claim" signal output of AND gate 50 that occurs with thesimultaneous appearance of the three input signals to that gate isutilized to provide a key depressed indication to the attack/decaycircuitry of the tone generator (and to percussive controls, ifdesired), as well as to provide its previously recited functions ofsetting flip-flop S3 and resetting counter 55.

The assignment logic embodiment of FIGS. 7A and 78 may be associatedwith only a small number of tone generators (twelve, in the examplepreviously given), the exact number being selected in view of the costlimitations and the likely maximum number of keys that normally may beactuated simultaneously. In that case, each tone generator must supplyevery desired frequency corresponding to every note in every octave thatmay be played on the electronic organ.

FIG. 8A illustrates, in block diagrammatic form, an example of asuitable tone generator for generating the frequencies required for thenotes selected on the organ keyboards. Appropriate frequencies areproduced by properly addressing a memory unit containing amplitudesamples of the desired waveform obtained at uniformly spaced points intime. Since the sample points are uniformly spaced in time, rather thanuniformly spaced on the basis that an integral number of samples bepresent per cycle for each note frequency, the phase angle betweensample points varies according to the frequency of the note to begenerated. In a broader sense, the tone generator system of FIG. 8Ademonstrates the teachings of the present invention with regard toaddressing a memory unit at selectively controlled rates.

In implementing the memory addressing system of the present invention,the keyboard counter 1 is preferably provided with a note or key countersection 2 having at least one additional normally unused count that isto precede the initial count representing the sequence of keys and notesassociated therewith. This redudant count, which is readily provided bymerely employing a counter of greater capacity than is needed to handlethe minimum count, is utilized to provide a start pulse which precedesthe count that occurs each time the keyboard counter is reset to zero.Such a start pulse in the keyboard pulse train may, for example, beassigned to an imaginary key approximately two octaves below the lowestnote in each manual. Thus, this start pulse is the first pulse in thescan, for the illustrative example of scanning from low frequencies tohigh frequencies on each keyboard, and occurs automatically with resetof the counter 1. The start pulse is applied to a flip-flop 100 for apurpose which will be explained presently. In addition the zero count,or count designating the reset, of octave section 3 of keyboard counteris supplied to the other input terminal of flip-flop 100. A memory unit101, which is to be addressed at any of a number of selectivelycontrolled rates, is preferably a read-only memory containing thedigital amplitude values at predetermined sample points of a singlecycle of the comlex periodic waveform to be produced for all notefrequencies. That is to say, the same complex periodic waveform is to bereproduced for each note played, the only difference being that thephase angle between sample points stored in memory 101 will differaccording to the frequency at which the complex waveform is reproduced.

Before proceeding with a description of the system of FIG. 8A and itsoperation, concurrent reference is made to FIG. 9 illustrating a typicalcomplex waveshape of the type that might be produced by a pipe organ.The waveshape shown in FIG. 9 has been sampled at a multiplicity ofpoints, shown as vertical lines in the Figure, to obtain the amplitudedata to be stored in memory unit 101. It is only these uniformly spacedsamples of amplitude that are stored in the memory and these may bestored in absolute form or in incremental form. In the former case, thedata accessed is the actual amplitude of the output waveform at therespective sample point (i.e., with respect to a zero level at theabscissa). In the case of incremental amplitude information, however,the amplitude at each sample point as stored in memory 101 is simply thedifference in amplitude between the amplitude of the present sample .andthe amplitude of the immediately preceding sample. Each of the amplitudesamples stored in the memory preferably comprises a digital word ofapproximately seven or eight bits.

Memory unit 101 may be a microminiature diode array of the typedisclosed by R. M. Ashby et al. in U. S. Pat. No. 3,377,513, issued Apr.9, 1968 and assigned to the same assignee as the present invention. Thearray may, for example, contain an amplitude representation of thedesired waveform in the form of an eight bit binary word at each of 48or more sample points. Such a capacity permits the storage of up to onehundred 28 amplitude levels in addition to a polarity (algebraic sign)bit. In any event, the capacity of memory 101 should be sufficient toallow faithful reproduction of each of the note frequencies.

The system for addressing memory 101 includes a storage register 102which when reset contains a number representing the phase angle betweensample points for the lowest note frequency to be produced by the tonegenerator. The storage register 102 is connected in a recirculating loop103 which includes a multiplier 104 and a gate 105. The purpose of themultiplier is to successively multiply the contents of the storageregister by the twelfth root of two (i.e., 2"") for computation of thephase angles between sample points of the complex waveform stored inmemory 101 for every note frequency in the entire range of frequenciescapable of being generated by the organ. This follows from the fact thatin the equal interval, or even temperament, musical scale the notefrequencies differ from one another by 2 The required computation may beperformed in either a serial or parallel arrangement. For example, thestorage register may be l2-bits long, and for serial operation, mayrecirculate once each 12 bit times. In such a case, the multiplier 104is specifically constructed and arranged for serial operation. Thekeyboard counter octave section 3 (FIG. 1) advances once each twelve bittimes, and hence, the storage register recirculates once each count ofthe octave section counter.

The computation of phase angle need not be performed in a serial format,however. Referring to FIG. 88, a parallel arrangement is shown in whichthe storage register 102 is connected to a scaling circuit 120 which, inturn, is coupled to an adder 121 in the recirculating loop 103. Thetwelfth root of two is approximately equal to 1.000011110011], base 2,which is equivalent to (1 2 -2 +2 2 The scaling circuit 120 is simply aset of multipliers. The adder 121 is preferably a cascaded network ofparallel two input adders adapted to receive the outputs of the sealers.The phase angle number constituting the result of the addition is thenrecirculated back to the storage register 102.

Returning now to FIG. 8A, flip-flop is reset upon application of zerocount of the octave section counter thereto, and the reset output of theflip-flop also serves to reset the storage register 102. Uponapplication of the start pulse of the multiplexed signal to theflipflop, the latter is switched to remove the register reset and toopen the gate 105a in recirculating loop 103, thereby allowing theregister contents to be multiplied by 2 and re-stored in the register.

The phase angle number which is thereby calculated with each advance ofthe keyboard count, and which represents a different phase angle betweenamplitude samples of the waveform stored in memory 101 for eachdifferent frequency, is always available when a note generator iscaptured and is assigned to generate a particular note frequency. Whenthe modulo 384 counter 55 in the assignment logic associated with thecaptured note generator is reset to zero, the phase angle numberavailable from the storage register 102, which is the correct phaseangle for the selected note, because of the synchronization between thephase angle calculation and the keyboard count, is read into a phaseangle register 108, and this occurs each time that modulo 384 counter 55goes to zero. To that end, the zero count of counter 55 is applied to aflip-flop 105 (e.g., a one-shot) which is normally set to preventpassage of the phase angle number through an associated gate 106, butwhich is reset to open the gate 106 to permit passage of the phase anglenumber therethrough to the phase angle register 108 when the flipflop105 is reset by the zero count of counter 55.

Quite clearly, the overall phase angle calculator and the read-onlymemory 101 may be shared by all of the tone generator 28. Each tonegenerator is addressed individually in the sequence of addressing alltone generators. For that reason, an auxiliary sampling clock (notshown) may be utilized which comprises a clock rate, provided by themaster sampling clock, successive clock pulses of which are directed tothe series of tone generators. The sampling clock addressed to a giventone generator is thus at a rate comprising the pulse repetition rate ofthe master sampling clock divided by the number of tone generatorsprovided in the system. Furthermore, since the same read-only memory maybe addressed by all of the tone generators, an accumulator 104aassociated with the memory may be a composite structure associated withappropriate gating circuitry related to each tone generator foraccumulating the information read from memory 101 in response toaccessing thereof by a given tone generator.

Once each sampling clock time, as determined by the auxiliary samplingclock source controlled by the master clock, the phase angle valuestored in the respective phase angle register 108 is added to thepreviously stored value in a sample point address register 109. Anaddress decoder 110 decodes preselected bit positions of the countestablished in register 109 to effect addressing of memory unit 101. Itis important to note that during addressing of memory 101, it is therate at which the value of the sample point address register 109increases, and not the absolute value of its contents, which issignificant in the control of the rate of readout of the memory 101, andthus in the control of the frequency of the note produced by the giventone generator.

In this manner, once each clock time the phase angle number, comprisinga digital binary word, is added to the sample point address registervalue and correspondingly, for each such clock time, the amplitude datain the memory location corresponding to the sample point address thencontained in register 109 (as de 1 coded bydecoder 110) is accessed. Asa practical manner, only a relatively small, finite set of amplitudescan I be stored in memory 101 because of practical limitations on itscapacity, and thus only a finite number of addresses is available.Furthermore, each register must "be of a finite, practical length. Inparticular, the length of each register must be determined by theaccuracy with which the frequency of the note is to be generated. Thefrequency actually produced is precisely the value of the phase anglemultiplied by the clock rate at which the contents of the phase angleregister are supplied to the address register 109. Thus, as the phaseangle corresponding to the specific frequency changes, when a differentnote is selected, the rate at which the memory unit 101 is addressedalso changes. In particular, it will be observed that the sample pointaddress register 109 is incremented by the value of the phase anglenumber at each auxiliary clock time. That is to say, once each clocktime, the phase angle number is added to the sample point addressregister. Only a relatively small number of bits in the region of leastsignificance of the address register contents are used to designate thesample point addressed in memory 101 and these bits are arranged to beincremented at a rate which depends upon the phase angle number.Accordingly, for small phase angle numbers, no new address may bespecified for several increases in the address-identifying number. Atthe uppermost note frequency, on the other hand, a sample point addressin the memory is identified, and the memory is addressed for retrievalof the data contained in the specified location, for each increment ofthe address register dictated by the phase angle number. For lowerfrequencies, the incrementing of the sample point address register issuch that new addresses are identified only after a corresponding numberof repetitions of the phase angle number at the fixed clock frequency.In the embodiment of FIG. 8A, the same effect is achieved by use of anaddress decoder 110. The digital words thus read from memory unit 101are supplied to an accumulator 1042 which provides a digitalrepresentation of the waveform at selected sample points over a cycle ofthe waveform and at a frequency corresponding to the note to bereproduced. As above described, this digital waveform representation mayitself be operated upon for waveshape control (for exam ple, attack anddecay) and is subsequently supplied to a digital-to-analog converter forproducing an analog signal suiable for driving the acoustical outputmeans, such as audio speakers, of the organ.

What is claimed is:

1. An electronic organ including a keyboard having a plurality of keysrespectively associated with notes of themusical scale, said keys beingoperable, when actuated, to develop signals for calling forthrespectively associated notes as audible tones of the desired notefrequencies from said organ, and a tone generator said tone generatorcomprising:

a memory storing amplitude samples of a waveform to be reproduced at thedesired note frequencies, said amplitude samples of the waveform beingtaken at points uniformly spaced in time over a cycle thereof,

clock means establishing a fixed rate of accessing amplitude samples ofsaid waveform from said memory,

means for developing a succession of phase angle numbers respectivelycorresponding in value to the frequencies of the notes of the musicalscale available to be called forth selectively by actuation ofcorresponding ones of the keys, and 7 means responsive to a signaldeveloped by the actua- 2. An electronic organ as recited in claim 1wherein said number developing means includes:

means for establishing a first number corresponding to a lowestfrequency note available to be reproduced, and

means for successively increasing the first and each successive numberby a common factor to develop a set of numbers differing respectively insuccession by the common factor, thereby to correspond to successivenote frequencies of the musical scale, for all note frequencies to besynthesized.

3. An electronic organ as recited in claim 2 wherein said responsivemeans includes:

a note frequency number register for storing the numbers correspondingto the selected note, and an address register for adding the stored,corresponding number to the contents of said address register at thefixed frequency of said fixed frequency generator, the content of saidaddress register thereby increasing at a rate corresponding to the fixedfrequency and the selected number and establishing the rate ofaddressing said memory. 4. A tone generator for synthesizing frequenciesof the notes of the musical scale in an electronic musical instrument,the instrument including means for selecting the notes to besynthesized, said generator comprism nemory means for storing amplitudevalues of a waveform to be reproduced at the desired note frequencies,said amplitude values of the waveform being taken at uniformly spacedpoints in time over one cycle of the waveform,

a fixed frequency generator,

means for developing a succession of numbers respectively correspondingin value to the frequencies of the notes of the musical scale availablefor selection, and

means responsive to the selection of a particular note to be synthesizedby said generator for responding to the number developed by saiddeveloping means for that note frequency and the fixed frequency of saidfixed frequency generator, thereby to address said memory at a ratecorresponding to the frequency of said generator and the number for thecorresponding note frequency, thereby cyclically to read out the storedamplitude values from said memory for synthesizing the selected notefrequency.

5. An electronic organ as recited in claim 4 wherein said numberdeveloping means includes:

means for establishing a first number corresponding to a lowestfrequency note available to be reproduced, and

means for successively increasing the first and each successive numberby a common factor to develop a set of numbers differing respectively insuccession by the common factor, thereby to correspond to successivenote frequencies of the musical scale, for all note frequencies to besynthesized.

6. An electronic organ as recited in claim 5 wherein said responsivemeans includes:

a note frequency number register for storing the establishing the rateof addressing said memory.

1. An electronic organ including a keyboard having a plurality of keysrespectively associated with notes of the musical scale, said keys beingoperable, when actuated, to develop signals for calling forthrespectively associated notes as audible tones of the desired notefrequencies from said organ, and a tone generator said tone generatorcomprising: a memory storing amplitude samples of a waveform to bereproduced at the desired note frequencies, said amplitude samples ofthe waveform being taken at points uniformly spaced in time over a cyclethereof, clock means establishing a fixed rate of accessing amplitudesamples of said waveform from said memory, means for developing asuccession of phase angle numbers respectively corresponding in value tothe frequencies of the notes of the musical scale available to be calledforth selectively by actuation of corresponding ones of the keys, andmeans responsive to a signal developed by the actuation of any one ofsaid keys for selecting the corresponding phase angle number, andresponsive to said clock means for addressing the sample points to beaccessed from said memory at a rate in proportion to the corresponding,selected phase angle for the note frequency associated with eachactuated key, to cyclically reproduce the stored waveform at a frequencycorresponding to the note frequency associated with the respective,actuated key.
 2. An electronic organ as recited in claim 1 wherein saidnumber developing means includes: means for establishing a first numbercorresponding to a lowest frequency note available to be reproduced, andmeans for successively increasing the first and each successive numberby a common factor to develop a set of numbers differing respectively insuccession by the common factor, thereby to correspond to successivenote frequencies of the musical scale, for all note frequencies to besynthesized.
 3. An electronic organ as recited in claim 2 wherein saidresponsive means includes: a note freqUency number register for storingthe numbers corresponding to the selected note, and an address registerfor adding the stored, corresponding number to the contents of saidaddress register at the fixed frequency of said fixed frequencygenerator, the content of said address register thereby increasing at arate corresponding to the fixed frequency and the selected number andestablishing the rate of addressing said memory.
 4. A tone generator forsynthesizing frequencies of the notes of the musical scale in anelectronic musical instrument, the instrument including means forselecting the notes to be synthesized, said generator comprising: memorymeans for storing amplitude values of a waveform to be reproduced at thedesired note frequencies, said amplitude values of the waveform beingtaken at uniformly spaced points in time over one cycle of the waveform,a fixed frequency generator, means for developing a succession ofnumbers respectively corresponding in value to the frequencies of thenotes of the musical scale available for selection, and means responsiveto the selection of a particular note to be synthesized by saidgenerator for responding to the number developed by said developingmeans for that note frequency and the fixed frequency of said fixedfrequency generator, thereby to address said memory at a ratecorresponding to the frequency of said generator and the number for thecorresponding note frequency, thereby cyclically to read out the storedamplitude values from said memory for synthesizing the selected notefrequency.
 5. An electronic organ as recited in claim 4 wherein saidnumber developing means includes: means for establishing a first numbercorresponding to a lowest frequency note available to be reproduced, andmeans for successively increasing the first and each successive numberby a common factor to develop a set of numbers differing respectively insuccession by the common factor, thereby to correspond to successivenote frequencies of the musical scale, for all note frequencies to besynthesized.
 6. An electronic organ as recited in claim 5 wherein saidresponsive means includes: a note frequency number register for storingthe numbers corresponding to the selected note, and an address registerfor adding the stored, corresponding number to the contents of saidaddress register at the fixed frequency of said fixed frequencygenerator, the content of said address register thereby increasing at arate corresponding to the fixed frequency and the selected number andestablishing the rate of addressing said memory.